1. Field of the Invention
The present invention relates to semiconductor memory element, and more particularly to a memory element comprised of a charge transfer device, a charge storage device, and one or more semiconductor junctions.
2. Description of Related Art
It is desired to store data such that it is not necessary to cycle a cell to periodically refresh the state of the data. An SRAM (Static Random Access Memory) is one such type of memory device which does not require periodic refreshing of charge stored in the cell. An SRAM typically requires between four (4) and six (6) individual transistors in each memory cell, and hence consumes a relatively large area on the chip as compared with a single (1) transistor DRAM (Dynamic Random Access Memory) cell. However, a DRAM cell requires periodic refreshing of the charge to retain the data stored in that DRAM cell. xe2x80x9cStructure and Process for Fabricating a 6F2 DRAM Cell Having Vertical MOSFET and Large Trench Capacitancexe2x80x9d referring to FIGS. 1 and 2 thereof a deep storage trench (DT) with a substantially rectangular design is formed in a semiconductor substrate. The DT has a capacitor formed in the bottom region thereof. A vertical MOSFET is formed in the region of the DT. The capacitor includes an N+ plate formed about the exterior of the trench. There is an N band region formed in the substrate abutting the deep trench and the upper surface of the N+ plate. A storage node dielectric (26) lines the walls of the DT and the node electrode (28) of the capacitor composed of N+ polysilicon is formed in the DT inside the storage node dielectric (26). Before or after forming the storage node electrode (28) in the bottom portion of the trench, a relatively thick collar (30) is formed above the N+ doped capacitor plate (22) so as to provide isolation between the capacitor and the MOSFET. A polysilicon strap region (38) is formed on the sidewalls of the DT above the relatively thick collar (30). Above the storage node electrode (28) and the polysilicon strap region (38), a Trench Top Oxide (TTO) (32) is formed. Above the TTO the DT is lined with a gate oxide layer (34) and a N+ polysilicon gate conductor (GC) (36) composed of doped polysilicon is formed. FIG. 14 shows, an xe2x80x9coutdiffused strapxe2x80x9d formed adjacent to the strap region (38) in a P-well (66) with a bitline diffusion (64) thereabove. Note that the P-well 66 is isolated from the N+ doped capacitor plate (22) by an N band region (24). As shown in FIGS. 3 and 14, on one side of the DT, the GC, the TTO, the strap polysilicon and an upper corner of the storage node polysilicon and the collar have been etched away and then filled with oxide cap (42) formed with a material such as CVD oxide. While there are similarities, as will be described below, the structure is substantially different from the structure of the present invention. In particular, as dimensional constraints force narrower capacitor dimensions, we have found that the thickness of the collar around the upper portion of the capacitor is a problem since it increases the width of capacitor and a solution to that dimensional problem is important.
More importantly, a solution to the problem of refreshing of DRAM cells is needed. There is nothing in the above patent (422) suggests a self-refreshing DRAM cell design. Instead, the patent (422) is designed to avoid providing any parasitic effects or punchthrough and the P-well doping concentration is kept low enough to prevent reverse bias junction leakage between the buried-strap and the P-well. The Mandelman et al. design avoids the effects which are achieved by the present invention.
Gruening et al. xe2x80x9cA Novel Trench DRAM Cell with a VERTical Access Transistor and Buried Strap (VERIBEST) for 4 Gb/16 Gbxe2x80x9d IEDM, pp 25-28, IEEE (1999) describes a doping profile of the P-well selected to maintain a concentration below 7 times 10 to the 17th per cm3 in proximity to the buried-strap which leads away from the teachings of the present invention as is typical of conventional DRAM design, as is well known by those skilled in the art.
Commonly assigned U.S. Pat. No. 6,236,077 of Gambino et al. for xe2x80x9cTrench Electrode with Intermediate Conductive Barrier Layerxe2x80x9d shows a strap formed above the collar of a trench capacitor and discusses the fact that materials can be used in the capacitor structure to minimize parasitic effects.
Commonly assigned U.S. Pat. No. 6,259,129 of Gambino et al. for xe2x80x9cStrap with Intrinsically Conductive Barrierxe2x80x9d describes a buried-strap which resides over the trench electrode (capacitor node).
Commonly assigned U.S. Pat. No. 6,265,279 of Radens et al for xe2x80x9cMethod for Fabricating a Trench Capacitorxe2x80x9d describes a trench capacitor formed as part of a trench capacitor memory cell wherein parasitic transistor leakage (which in the past could have been reduced by using a thicker collars) has been reduced by implanting dopant into sidewalls of the trench extending outwardly of the trench to disrupt the parasitic transistor.
Heretofore, it is clear that the objective in the art has been to suppress parasitic transistors and currents in the regions of doped semiconductor regions surrounding trench capacitors.
An object of this invention is to provide a dense DRAM type of memory cell which does not require periodic refreshing of the charge.
In particular, there are problems as follows:
a) refreshing a DRAM memory cell without wordline/bitline (WL/BL) cycling;
b) offsetting DRAM memory cell (junction) leakage currents to obtain data retention and product operating margins;
c) relaxing storage node electrode leakage requirements and/or storage capacitance requirements.
An advantage of this invention is that it provides a self-refreshing DRAM memory cell with two stable static states of operation. In the first stable static state, the DRAM memory cell automatically holds a binary one voltage level by exploiting parasitic leakage current between the storage node electrode and the buried plate electrode. In the second stable static state, the DRAM memory cell automatically holds a binary zero (0) by exploiting parasitic leakage current between the storage node electrode and the P-well.
In accordance with this invention, controlled leakage currents are used to provide automatic-refreshing in a xe2x80x9cSelf-Refreshing Single-Capacitor Random Access Memory (SSRAM)xe2x80x9d structure as follows:
a) for a stored binary one (1), there is a controlled gate assisted punchthrough current between node diffusion and plate;
b) for a stored binary zero (0), there is a controlled junction leakage current to the P-well.
This invention provides a new cell structure that provides automatic static refreshing of charge to maintain the stored data. Thus the standard DRAM dynamic charge refreshing cycle may be eliminated. Optionally, the standard dynamic charge refreshing cycle may be used, but the storage capacitance, and accumulated process/structural complexity may be reduced.
In accordance with this invention the buried plate is biased at a voltage of about +1.2V and the P-well is biased at a voltage level of about xe2x88x920.5V or below.
In accordance with another aspect of this invention, the structure is capable of punchthrough between the strap and plate during the presence of a stored binary one (1) by forming the N+ strap in close proximity to the N+ plate and selection of the associated junction profiles including the buried-strap outdiffusion, P-well and buried plate.
Further in accordance with this invention, the distance between the strap outdiffusion region in the P-well and the N+ plate electrode is between about 50nm and about 300 nm. The optimum distance is dependent upon doping concentration between the node electrode and the plate. Punchthrough leakage current through the P-well between the strap/storage node electrode and the buried plate electrode refreshes the charge which represents the stored binary one (1).
In addition, the P-well doping profile is graded to induce junction leakage between the strap and the P-well during the presence of a stored level binary zero (0). The doping of the P-well to a concentration of dopant above 6E17/cm3 induces junction leakage between the N+ buried-strap and the P-well. Thus the doping constraint on the P-well adjacent to the strap diffusion, which must be observed in a conventional DRAM, is relaxed and/or eliminated.
Challenges in connection with this invention are as follows:
a) Control of strap-to-plate depth and P-well profile.
b) Leakage and reliability of the full plate voltage across the thin node dielectric layer.
In accordance with this invention, a device is provided by starting with a deep trench having sidewalls and a bottom that is formed in a semiconductor substrate. The trench has upper, central and lower portions. A buried plate electrode of a capacitor which is formed in the substrate, surrounding the lower portion of the deep trench, is doped with a first dopant type and is separated by an interface from a well region that surrounds the upper and central portions of the deep trench. The well region is doped with an opposite dopant type. A cap region is formed above the well doped with the first dopant type. A node dielectric layer covers the sidewalls and the bottom of the lower and central portions of the deep trench and the node dielectric layer defines a node electrode space in the lower and central portions of the deep trench. The node electrode space is filled with a node electrode of the capacitor. The node electrode is doped with the first dopant type. A buried-strap region space, preferably in the form of a node dielectric layer recess, is formed about the upper portion of the node electrode. The strap region space is filled with a buried-strap. A trench top dielectric layer is formed above the node electrode and the buried-strap covering the top of the central portion of the deep trench. A gate oxide layer is formed on the sidewall surfaces of the upper portion of the deep trench. A gate electrode fills the space in the deep trench defined by the gate oxide layer. An outdiffusion region doped with the first dopant type is formed in the well region proximate to the buried-strap. The cell includes an FET transistor formed above the buried-strap and connected thereto having binary states comprising a first state and an opposite state of operation. The cell includes a punchthrough device formed in the well between the outdiffusion region and the interface. The punchthrough device provides a punchthrough current which provides self-refreshing current in the cell between the well and the plate in the first state of operation of the cell. In the opposite state of operation of the cell, the punchthrough device provides reverse bias junction leakage in the cell between the buried-strap and the well refreshing the opposite state of operation of the cell.
Preferably, in a binary one stable state, the device automatically holds a binary one by exploiting leakage between the node electrode and the buried plate electrode through an expanded outdiffusion depletion region in the well surrounding the outdiffusion region and an expanded depletion region in the well between the interface and the outdiffusion depletion region which merge. In a binary zero stable state, the device automatically holds a binary zero by preventing leakage between the node electrode and the buried plate electrode through a contracted outdiffusion depletion region in the well that surrounds the outdiffusion region and a contracted depletion region in the well between the interface and the outdiffusion depletion region that are separate regions in the well.
Preferably, the outdiffusion region is located from about 50 nm to about 300 nm from the interface between the well region and the buried plate electrode.
Preferably, the node dielectric layer and the buried-strap have a thickness from about 2 nm to about 10 nm.
Preferably, the outdiffusion region is juxtaposed with the buried-strap and centered thereon.
Preferably, the buried-strap extends about 160 nm above the interface between the well region and the plate electrode.